Bufferless Routeing in Network-On-Chip
Mentor: Dr. John Jose (Dept. of CSE, IIT Guwahati)
Collaborators: Nandan Bedekar, N Hariharan
On-chip interconnection networks are gaining popularity due increase in the number of cores on a processor chip. These networks allow multicore processing without the delays introduced by direct wiring. We modified the network traffic simulator BookSim 2.0 to study the properties of bufferless routers. In particular, we encoded the CHIPPER architecture.
